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(15) Make

make

A tool for managing collections of files with dependancies (typically program source code).

Make gets its knowledge of how to build your program from a file called makefile (or Makefile). Make is traditionally used for preprocessing, compiling and linking of source code to build programs, but can also be used for other purposes. It streamlines the process of compiling complex programs by automatically determining which source files of a program need to be recompiled and/or linked. Only the files which are out of date with respect to their dependants are rebuilt.

A makefile consists of rules with the following format:

target: dependencies ...
     commands
     ...

myappl: srcfile1.o srcfile2.o srcfile3.o
    cc -o myapp1 srcfile1.o srcfile2.o srcfile3.o -lm
srcfile1.o: scrfile1.c myinclude.h
    cc -c srcfile1.c 
srcfile2.o: scrfile2.c myinclude.h
    cc -c srcfile2.c 
srcfile3.o: scrfile3.c myinclude.h
    cc -c srcfile3.c 
clean:
    rm -f myapp1 srcfile1.o srcfile2.o srcfile3.o

Note: You need to put a tab character at the beginning of each command line.

It is usually easiest to start with an existing makefile and edit it for a new application. Using the name Makefile is preferred - it appears near the top of the directory listing.

Using Macros (Variables) in Makefiles

Macros make it easier to define commands and sets of dependancies, and simplify your makefile

Here is an example macro defintion:

OBJS=srcfile1.o srcfile2.o srcfile3.o

To use this macro type $(OBJS)

Here is a new version of the makefile

OBJS=srcfile1.o srcfile2.o srcfile3.o

myappl: $(OBJS)
    cc -o myapp1 $(OBJS) -lm
srcfile1.o: scrfile1.c myinclude.h
    cc -c srcfile1.c 
srcfile2.o: scrfile2.c myinclude.h
    cc -c srcfile2.c 
srcfile3.o: scrfile3.c myinclude.h
    cc -c srcfile3.c 
clean:
    rm -f myapp1 $(OBJS)

$(CC) - C compiler command (cc)
$(FC) - Fortran compiler command (f77)
$(CFLAGS) - C compiler flags
$(FFLAGS) - Fortran compiler flags

You can add macros to the command line : make myapp1 CC=gcc

Suffixes

Make has many default rules for creating one type of file from another. There are additional built-in macros to make this easier. ($< stands for the file that triggered the rule, i.e. the .c or .f file). The mechanism uses the filename suffix convention used by most compilers.
For example, to compile a C source code file prog.c and create the object code file prog.o, we need to construct the command:
cc -c prog.c
The built-in rule which does this is:

.SUFFIXES: .c
.c.o:
    $(CC) $(CFLAGS) -c $<
.f.o:
    $(FC) (FFLAGS) -c $<

You can add your own default rules to process files in any way that uses the suffix convention, simplifying the explicit commands in the Makefile. Use the command make -p to see a list of all predefined suffixes and macros.